Test bus interfaces exist which allow serial data to be shifted in and out of integrated circuits to facilitate testing of the logic in the device. These buses are designed primarily to transfer a single pattern of serial data into and out of a selected scan path surrounding the circuit under test once per shift operation. Depending on the complexity of the circuit, potentially thousands or hundreds of thousands of shift operations may be required to fully test the circuit. Having to repeat a shift operation multiple times to transfer test data patterns into and out of the circuit being tested is time consuming.